The present inventive concept relates to semiconductor devices and, more particularly, to interconnection structures for semiconductor devices.
Semiconductor devices having increased integration density are needed in order to satisfy consumer demand for high perfoimance low cost devices. In the case of general two-dimensional or planar semiconductor memory devices, the level of integration may be primarily determined by the area required for each unit cell of the device. In such devices, the integration density is primarily increased by decreasing the width of the pattern used to form such unit cells.
However, when the width of the pattern is decreased, various technical difficulties may arise. For example, when the width of the pattern is decreased to 50 nm or less, new lithography arts such as immersion lithography, EUV lithography, or double patterning art may be required to form the pattern.
In addition, in order to rapidly transmit electric signals through the semiconductor device, the resistance of the interconnection needs to be kept low. Since the resistance of the interconnection is inversely proportional to the cross-sectional area of the interconnection, when the width of the interconnection is decreased, the thickness of the interconnection may need to be increased in order to maintain a low resistance value. However, when the interconnections are disposed at narrow intervals as is often the case, for example, with bit lines of semiconductor memory devices, an increase in thickness of the interconnection may cause an increase in capacitance or coupling between the interconnections. This capacitance/coupling may generate secondary technical problems such as RC-delay and crosstalk between interconnections that may degrade the performance of the semiconductor device.